We demonstrate the existence of two different degradation mechanisms for 100 V GaN transistors submitted to off-state stress. When the devices are stressed in strong pinch-off conditions, a high electric field falls on the dielectric between the source field plate and the channel, and a time dependent dielectric breakdown is observed. On the other hand, for weaker pinch-off, hot electrons trapping at the passivation surface can lower the electric field, leading to longer TTF. A second degradation mode is also observed, consisting in the gradual increase in off-state current, ascribed to positive charge trapping at defects spots.

Evidence for double degradation regime in off-state stressed 100 V GaN transistors: From dielectric failure to subthreshold current increase

Fraccaroli R.;Fregolent M.;Boito M.;De Santi C.;Canato E.;Rossetto I.;Meneghesso G.;Zanoni E.;Meneghini M.
2025

Abstract

We demonstrate the existence of two different degradation mechanisms for 100 V GaN transistors submitted to off-state stress. When the devices are stressed in strong pinch-off conditions, a high electric field falls on the dielectric between the source field plate and the channel, and a time dependent dielectric breakdown is observed. On the other hand, for weaker pinch-off, hot electrons trapping at the passivation surface can lower the electric field, leading to longer TTF. A second degradation mode is also observed, consisting in the gradual increase in off-state current, ascribed to positive charge trapping at defects spots.
2025
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3552254
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