BEVILACQUA, ANDREA
BEVILACQUA, ANDREA
Dipartimento di Ingegneria dell'Informazione - DEI
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS
2025 Fietta, Edoardo Baiesi; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm PSAT and 40.1% PAE
2025 Pecile, Davide; Gambarucci, Alberto; Kokorovic, Stefan; Bevilacqua, Andrea
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers
2025 Baiesi Fietta, Edoardo; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators
2025 Bevilacqua, Andrea; Mazzanti, Andrea
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies
2024 Tomasin, Lorenzo; Iesurum, Agata; Gobbo, Andrea; Neviani, Andrea; Bevilacqua, Andrea
Analysis and Design of Coupled PLL-Based CMOS VCOs
2024 Iesurum, A; Manente, D; Padovan, F; Bassi, M; Bevilacqua, A
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
2024 Tomasin, Lorenzo; Vogrig, Daniele; Neviani, Andrea; Bevilacqua, Andrea
Analysis of CMRR in Doubly-Tuned Transformer Baluns
2024 Bevilacqua, Andrea; Mazzanti, Andrea
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
2024 Bellemo, Luca; Bevilacqua, Andrea
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
2023 Manente, Davide; Quadrelli, Fabio; Padovan, Fabio; Bassi, Matteo; Mazzanti, Andrea; Bevilacqua, Andrea
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
2022 Tomasin, L; Andreani, P; Boi, G; Padovan, F; Bevilacqua, A
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
2022 Quadrelli, F.; Manente, D.; Seebacher, D.; Padovan, F.; Bassi, M.; Mazzanti, A.; Bevilacqua, A.
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
2022 Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices
2022 Modolo, N.; De Santi, C.; Baratella, G.; Bettini, A.; Borga, M.; Posthuma, N.; Bakeroot, B.; You, S.; Decoutere, S.; Bevilacqua, A.; Neviani, A.; Meneghesso, G.; Zanoni, E.; Meneghini, M.
Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing
2022 Shi, Cy; Song, My; Gao, Zy; Bevilacqua, A; Dolmans, G; Liu, Yh
A 20-GHz Class-C VCO with 80-GHz Fourth-Harmonic Output in 28-nm CMOS
2021 Franceschin, A.; Quadrelli, F.; Padovan, F.; Bassi, M.; Mazzanti, A.; Bevilacqua, A.
A Multichannel D-Band Radar Receiver with Optimized LO Distribution
2021 Bilato, A.; Issakov, V.; Mazzanti, A.; Bevilacqua, A.
Doubly-Tuned Transformer Networks: a Tutorial
2021 Bevilacqua, Andrea; Mazzanti, Andrea
Harmonic Oscillators in CMOS—A Tutorial Overview
2021 Andreani, Pietro; Bevilacqua, Andrea