BEVILACQUA, ANDREA
BEVILACQUA, ANDREA
Dipartimento di Ingegneria dell'Informazione - DEI
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS
2025 Fietta, Edoardo Baiesi; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE
2025 Pecile, Davide; Kokorovic, Stefan; Gambarucci, Alberto; Bevilacqua, Andrea
A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication
2025 Navarin, Lucrezia; Norling, Karl; Parenzan, Marco; Uran, Alexander; Ruzzu, Stefano; Rathinam, Krithika; Neviani, Andrea; Bevilacqua, Andrea
A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking
2025 Bellemo, Luca; Neviani, Andrea; Bevilacqua, Andrea
Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm PSAT and 40.1% PAE
2025 Pecile, Davide; Gambarucci, Alberto; Kokorovic, Stefan; Bevilacqua, Andrea
Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters
2025 Frassetto, Domenico; Cabizza, Stefano; Agostinelli, Matteo; Garbossa, Cristian; Spiazzi, Giorgio; Bevilacqua, Andrea; Neviani, Andrea
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers
2025 Baiesi Fietta, Edoardo; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators
2025 Bevilacqua, Andrea; Mazzanti, Andrea
A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs
2024 Grimaldi, Luigi; Iesurum, Agata; Boi, Giovanni; Versolatto, Fabio; Steffan, Giovanni; Padovan, Fabio; Koltsov, Heorhii; Bevilacqua, Andrea; Cherniak, Dmytro
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies
2024 Tomasin, Lorenzo; Iesurum, Agata; Gobbo, Andrea; Neviani, Andrea; Bevilacqua, Andrea
Analysis and Design of Coupled PLL-Based CMOS VCOs
2024 Iesurum, A; Manente, D; Padovan, F; Bassi, M; Bevilacqua, A
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
2024 Tomasin, Lorenzo; Vogrig, Daniele; Neviani, Andrea; Bevilacqua, Andrea
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology
2024 Zugno, Nicolò; Bevilacqua, Andrea
Analysis of CMRR in Doubly-Tuned Transformer Baluns
2024 Bevilacqua, Andrea; Mazzanti, Andrea
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
2024 Bellemo, Luca; Bevilacqua, Andrea
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers
2024 Fietta, Edoardo Baiesi; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
On the Efficiency of Output-Matched Radiofrequency Power Amplifiers
2024 Pecile, Davide; Kokorovic, Stefan; Gambarucci, Alberto; Bevilacqua, Andrea
On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting
2024 Bellemo, Luca; Spiazzi, Giorgio; Bevilacqua, Andrea
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
2023 Manente, Davide; Quadrelli, Fabio; Padovan, Fabio; Bassi, Matteo; Mazzanti, Andrea; Bevilacqua, Andrea