BEVILACQUA, ANDREA
BEVILACQUA, ANDREA
Dipartimento di Ingegneria dell'Informazione - DEI
A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs
2024 Grimaldi, Luigi; Iesurum, Agata; Boi, Giovanni; Versolatto, Fabio; Steffan, Giovanni; Padovan, Fabio; Koltsov, Heorhii; Bevilacqua, Andrea; Cherniak, Dmytro
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies
2024 Tomasin, Lorenzo; Iesurum, Agata; Gobbo, Andrea; Neviani, Andrea; Bevilacqua, Andrea
Analysis and Design of Coupled PLL-Based CMOS VCOs
2024 Iesurum, A; Manente, D; Padovan, F; Bassi, M; Bevilacqua, A
Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters
2024 Tomasin, Lorenzo; Vogrig, Daniele; Neviani, Andrea; Bevilacqua, Andrea
Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology
2024 Zugno, Nicolò; Bevilacqua, Andrea
Analysis of CMRR in Doubly-Tuned Transformer Baluns
2024 Bevilacqua, Andrea; Mazzanti, Andrea
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
2024 Bellemo, Luca; Bevilacqua, Andrea
On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers
2024 Fietta, Edoardo Baiesi; Seebacher, David; Ponton, Davide; Bevilacqua, Andrea
On the Efficiency of Output-Matched Radiofrequency Power Amplifiers
2024 Pecile, Davide; Kokorovic, Stefan; Gambarucci, Alberto; Bevilacqua, Andrea
On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting
2024 Bellemo, Luca; Spiazzi, Giorgio; Bevilacqua, Andrea
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
2023 Manente, Davide; Quadrelli, Fabio; Padovan, Fabio; Bassi, Matteo; Mazzanti, Andrea; Bevilacqua, Andrea
A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS
2023 Tomasin, L.; Vogrig, D.; Neviani, A.; Bevilacqua, A.
A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem
2023 Tomasin, L; Bevilacqua, A
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
2023 Zugno, N; Brandonisio, F; Niederfriniger, T; Bevilacqua, A
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
2022 Tomasin, L; Andreani, P; Boi, G; Padovan, F; Bevilacqua, A
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS
2022 Iesurum, Agata; Manente, Davide; Padovan, Fabio; Bassi, Matteo; Bevilacqua, Andrea
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
2022 Dartizio, Simone Mattia; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
2022 Buccoleri, Francesco; Dartizio, Simone M.; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Bevilacqua, Andrea; Bertulessi, Luca; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
2022 Quadrelli, F.; Manente, D.; Seebacher, D.; Padovan, F.; Bassi, M.; Mazzanti, A.; Bevilacqua, A.