Trapping and Reliability Properties of Al2O3 Gate Dielectrics Obtained with Stacked ALD Deposition

Vertical Gallium Nitride (GaN) transistors are among the most important technologies for the realization of high-voltage power switches with power electronics applications. Contrary to lateral high electron mobility transistors (HEMTs) in which the gate isolation is obtained with an epitaxially grown AlGaN barrier, vertical devices such as finFETs and trench MOSFETs employ a foreign oxide deposited during the device processing. Aluminum Oxide (Al2O3) is one of the most common choices for gate dielectrics, because of the high dielectric constant and band discontinuity, and the high deposition quality. In this work we will investigate the reliability and trapping properties of Al2O3/GaN MOS capacitors with 15 nm thickness obtained with different deposition techniques, including Thermal ALD (ThALD), Plasma ALD (PEALD), and layered structure composed by alternating 5 nm of ThALD, 5 nm of PEALD, and 5 nm of ThALD (Tadmor et al. 2024, JAP 135(8)). All the devices were submitted to an in-situ NH3 plasma pre-treatment prior to the oxide deposition. First, we investigated the robustness of the samples by performing a slow voltage ramp from 0 V up to the catastrophic failure of the devices. The results indicate that the pure ThALD samples show a higher gate current leakage (up to approximately 20 mA⁄(cm^2 )), that exponentially increases approximately from V_G=5 V up to the failure condition at V_G≈10 V. In the other hand, PEALD devices present a much lower gate leakage current, that reaches approximately 3 μA⁄(cm^2 ) before reaching the failure condition at gate bias V_G≈14 V. The layered wafers present an intermediate gate leakage current (up to 10 μA⁄(cm^2 )), with a failure voltage in line with the one obtained for the PEALD samples. This result can be explained by considering that the three oxides ideally form three capacitors in series; since the intermediate layer (PEALD) has the lowest conductivity and breakdown strength, it contributes to the suppression of the gate leakage current and increase of the failure voltage. Then, we studied the charge trapping in the oxide layers by analyzing the pulsed-CV characteristics under a quiescent bias of V_(G,QB)=5 V, to estimate the total number of trap states including interface and border traps (Fregolent et al. 2023, IRPS 2023). We found that the ThALD samples present lowest trapping (N_T=5×〖10〗^11 cm^(-2)), while PEALD has approximately one order of magnitude more trapping states N_T=3.7×〖10〗^12 cm^(-2). As expected, the layered oxide presents a defect concentration close to the values obtained one of the ThALD (N_T=1.2×〖10〗^12 cm^(-2)); this can be motivated by the fact that the electrons can be trapped within 2-3 nm from the Al2O3/GaN interface, therefore in the layered dielectric the trapping is confined in the low-trapping ThALD layer. In conclusion, we analyzed the gate oxide robustness and trapping properties of ALD-deposited Al2O3 with different techniques. We demonstrated that the layered gate oxide benefits from the low trapping induced by the ThALD layer and the high breakdown strength from the PEALD layer.