On-Wafer Dynamic Operation of Power GaN-HEMTs: Degradation Processes Investigated by a Novel Experimental Approach

This work presents a novel and versatile experimental setup for on-wafer dynamic high temperature operating lifetime (D-HTOL) and dynamic RON characterization of GaN power transistors on wafer level. The developed methodology allows to induce realistic hard switching stress condition and permits a fine tuning of all waveform parameters. This methodology was validated by analyzing the dynamic behavior in hard switching condition of 650 V HEMTs with p-GaN gate on wafer-level. Experimental results indicate that the dynamic RON degradation originates from trapping of electrons in the carbon-doped buffer due to the OFF-state component of the applied stress, and to surface trapping associated with the hard switching component.