Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors

This paper investigates the degradation of vertically aligned gallium nitride (GaN) nanowire (NW) arrays submitted to gate bias stress and UV light. Based on electrical tests and simulations, we demonstrate the existence of trapping processes that depend on the applied stress voltage VGstress and on the applied light during stress (wavelength, λ). We demonstrate the following original results: 1) for positive and negative VGstress conditions, no significant variation in dc characteristics is observed when the samples are stressed in dark and 2) when the devices are submitted to negative VGstress and to UV light, a positive variation in threshold voltage (Vth) is observed. The positive Vth shift is ascribed to the transfer and trapping of electrons from the gate metal to the oxide, promoted by UV light. We also evaluated the temperature dependence of the threshold voltage shift under UV light. We demonstrated an increased trapping at higher temperatures, indicating a role of thermionic processes in electron trapping. On the other hand, detrapping from oxide states proceeds through defect-mediated conduction, i.e., is limited by the number of available states.