This paper studies the impact of the properties of the SiN gate insulator on the dc and dynamic performance of AlGaN/GaN Metal Insulator Semiconductor High Electron Mobility Transistors (MIS-HEMTs). We compare the dynamic and transient behaviour of devices with identical epitaxial structure and different gate insulators: RTCVD-SiN (rapid-thermal-chemical-vapour-deposition) and PEALD-SiN (plasma-enhanced-atomic-layer-deposition). We demonstrate the following important results: (i) the gate leakage of devices with PEALD-SiN insulator is three orders of magnitude lower than that of samples with RTCVD-SiN; (ii) the use of PEALD-SiN reduces significantly the transistor threshold voltage hysteresis; (iii) both sets of samples show measurable threshold voltage shift when submitted to forward gate bias. In addition we demonstrate (iv) that the VTH shift is well correlated with the gate forward leakage and bias, for both sets of samples. This result indicates that trapping is induced by the injection of electrons in the gate insulator when a positive bias is applied to the gate; in PEALD SiN devices, the reduction of the gate (forward) leakage results in a significant decrease in VTH shift. © 2015 Elsevier Ltd.
Impact of gate insulator on the dc and dynamic performance of AlGaN/GaN MIS-HEMTs
ROSSETTO, ISABELLA;MENEGHINI, MATTEO;BISI, DAVIDE;BARBATO, ALESSANDRO;MARCON, DANIELA;MENEGHESSO, GAUDENZIO;ZANONI, ENRICO
2015
Abstract
This paper studies the impact of the properties of the SiN gate insulator on the dc and dynamic performance of AlGaN/GaN Metal Insulator Semiconductor High Electron Mobility Transistors (MIS-HEMTs). We compare the dynamic and transient behaviour of devices with identical epitaxial structure and different gate insulators: RTCVD-SiN (rapid-thermal-chemical-vapour-deposition) and PEALD-SiN (plasma-enhanced-atomic-layer-deposition). We demonstrate the following important results: (i) the gate leakage of devices with PEALD-SiN insulator is three orders of magnitude lower than that of samples with RTCVD-SiN; (ii) the use of PEALD-SiN reduces significantly the transistor threshold voltage hysteresis; (iii) both sets of samples show measurable threshold voltage shift when submitted to forward gate bias. In addition we demonstrate (iv) that the VTH shift is well correlated with the gate forward leakage and bias, for both sets of samples. This result indicates that trapping is induced by the injection of electrons in the gate insulator when a positive bias is applied to the gate; in PEALD SiN devices, the reduction of the gate (forward) leakage results in a significant decrease in VTH shift. © 2015 Elsevier Ltd.Pubblicazioni consigliate
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