In this article, we present the results of on-wafer short-term (24 h) stress tests carried out on 0.25- μm AlGaN/GaN HEMTs. Devices on-wafer were submitted to 24-h dc tests, at various gate and drain voltage values corresponding to dissipated power densities PD up to 40 W/mm, with estimated channel temperature 375 °C. GEN1 devices adopted a Ni/Pt/Au gate metallization and conventional plasma-enhanced chemical vapor deposition (PE-CVD) SiN passivation; in GEN2 devices, a modified gate metallization and a two-layer SiN passivation were adopted. When tested at Pd >25 W/mm, a substantial decrease of drain current ID and transconductance gm was measured in GEN1 HEMTs, without any significant shift of threshold voltage. Failure analysis revealed that Au and O interdiffusion took place from the sidewalls; Au gradually substituted Ni as a Schottky contact, while O, in the presence of high electric field, high temperature, and high current, promoted (Al)GaN oxidation and pitting. On the contrary, negligible degradation was found after high temperature storage of GEN1 devices without applied bias, up to 450 °C. In GEN2, process modification was effective in reducing the impact of this failure mechanism, resulting in only 5% gm decrease after 24 h at a junction temperature of 375 °C with PD = 38 W/mm. Results demonstrate the effectiveness of the adopted on-wafer screening methodology in identifying potentially dangerous failure mechanisms.
On-Wafer Fast Evaluation of Failure Mechanism of 0.25-μm AlGaN/GaN HEMTs: Evidence of Sidewall Indiffusion
Rzin M.;Meneghini M.;Rampazzo F.;Meneghesso G.;Zanoni E.
2020
Abstract
In this article, we present the results of on-wafer short-term (24 h) stress tests carried out on 0.25- μm AlGaN/GaN HEMTs. Devices on-wafer were submitted to 24-h dc tests, at various gate and drain voltage values corresponding to dissipated power densities PD up to 40 W/mm, with estimated channel temperature 375 °C. GEN1 devices adopted a Ni/Pt/Au gate metallization and conventional plasma-enhanced chemical vapor deposition (PE-CVD) SiN passivation; in GEN2 devices, a modified gate metallization and a two-layer SiN passivation were adopted. When tested at Pd >25 W/mm, a substantial decrease of drain current ID and transconductance gm was measured in GEN1 HEMTs, without any significant shift of threshold voltage. Failure analysis revealed that Au and O interdiffusion took place from the sidewalls; Au gradually substituted Ni as a Schottky contact, while O, in the presence of high electric field, high temperature, and high current, promoted (Al)GaN oxidation and pitting. On the contrary, negligible degradation was found after high temperature storage of GEN1 devices without applied bias, up to 450 °C. In GEN2, process modification was effective in reducing the impact of this failure mechanism, resulting in only 5% gm decrease after 24 h at a junction temperature of 375 °C with PD = 38 W/mm. Results demonstrate the effectiveness of the adopted on-wafer screening methodology in identifying potentially dangerous failure mechanisms.
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