Characterization of CMOS structures (0.6 μm process) submitted to HBM and CDM ESD stress test

In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 µm CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the turn-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).