HBM and CDM ESD stress test results in 0.6 μm CMOS structures

In this work, we present new results concerning electrostatic discharge (ESD) robustness in 0.6 μm device structure. Devices have been submitted to both HBM and socketed CDM (sCDM) ESD tests. A systematic failure analysis of the stressed structures has been carried out obtaining important information on the dependence of the behaviour of these on layout parameters. Typical LDD MOSFET devices show damages which mainly consist in drain/substrate junction spiking in correspondence of the contacts: breakdown of the less deeper P implant junction (n+-substrate) can be responsible for the observed degradation. Devices having P deeper implant source and drain are more resistant than the previous ones and their failure mechanisms consist in lateral spiking. For some large structures adopting lateral bipolar transistor with or without gate polysilicon over Field oxide technology, SEM analysis and emission microscopy clearly demonstrate that early ESD failures can be attributed to a non uniform current distribution within the structures