Heavy-Ion Induced Threshold Voltage Shifts in Sub 70-nm Charge-Trap Memory Cells

We investigate threshold voltage shifts induced by heavy ions in sub 70-nm charge-trap cells, based on TaN-Al(2)O(3)-SiN-SiO(2)-Si (TANOS) stack and compare the results with floating gate memories. Large shifts are observed, although to a smaller extent than in floating gate devices with similar feature size. Basic mechanisms leading to the heavy-ion induced charge loss/compensation in the storage layer are discussed, considering hole injection from the blocking and the tunnel oxide. The applicability of the transient conductive path and the transient carrier flux models developed for floating gate memories is evaluated as well.