We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of raw bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and, for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.
Annealing of Heavy-Ion Induced Floating Gate Errors: LET and Feature Size Dependence
BAGATIN, MARTA;GERARDIN, SIMONE;CELLERE, GIORGIO;PACCAGNELLA, ALESSANDRO;
2010
Abstract
We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of raw bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and, for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.
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