High-electric-field degradation phenomena are investigated in GaN-capped AlGaN-GaN HEMTs by comparing experimental data with numerical device simulations. Simulations indicate that the stress-induced amplification of gate-lag effects and the correlated gate-leakage-current reduction can be ascribed to the generation of acceptor traps at the gate-drain surface and/or in the device barrier. The drop in DC drain current observed after stress should rather be attributed to trap accumulation within the GaN buffer region. Only the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the observed degradation modes. Simulations suggest also that under power-state stress traps should accumulate over a wide region extending laterally from the gate edge towards the drain contact, whereas, under off-state stress, trap generation should rather take place in a narrower portion of the drain access region close to the gate edge and should be accompanied by a significant degradation of the channel transport parameters. Channel hot electrons and electric-field-induced strain-enhancement are finally suggested to play major roles in powerstate and off-state degradation, respectively.

Analysis of High-Electric-Field Degradation in ALGAN/GAN HEMTs

RAMPAZZO, FABIANA;MENEGHESSO, GAUDENZIO;ZANONI, ENRICO;
2007

Abstract

High-electric-field degradation phenomena are investigated in GaN-capped AlGaN-GaN HEMTs by comparing experimental data with numerical device simulations. Simulations indicate that the stress-induced amplification of gate-lag effects and the correlated gate-leakage-current reduction can be ascribed to the generation of acceptor traps at the gate-drain surface and/or in the device barrier. The drop in DC drain current observed after stress should rather be attributed to trap accumulation within the GaN buffer region. Only the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the observed degradation modes. Simulations suggest also that under power-state stress traps should accumulate over a wide region extending laterally from the gate edge towards the drain contact, whereas, under off-state stress, trap generation should rather take place in a narrower portion of the drain access region close to the gate edge and should be accompanied by a significant degradation of the channel transport parameters. Channel hot electrons and electric-field-induced strain-enhancement are finally suggested to play major roles in powerstate and off-state degradation, respectively.
2007
Proc. of WOCSDICE2007, 31th Workshop on Compound Semiconductor Devices and Integrated Circuits
9788861290884
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/1780183
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