In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 um CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.
Effects of ESD protections latch-up sensitivity of CMOS 4-stripe structure
MENEGHESSO, GAUDENZIO;ZANONI, ENRICO
1997
Abstract
In this paper, we present results on the influence of the turning on of ESD protection devices on the latch-up sensitivity of 0.35 um CMOS ICs. Moreover, we will show that layout details and circuit placement do have an influence on latch-up sensitivity, and that the presence of guard-rings greatly improves latch-up hardness.
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