A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking

The implementation of power switches in an integrated dc-dc converter always poses some design problems, especially when the switch must sustain voltage stresses above the voltage rating of the used transistors. This is further exacerbated when the switch must endure voltage stresses of both positive and negative polarity. This work describes a methodology to drive power switches, that are designed using stacks of lower voltage rating transistors, and operated over all four quadrants of the I-V plane, i.e., with both positive and negative current and voltage polarities. After illustrating the proposed driving strategy, an example is provided and a practical circuit implementation of the general driving strategy is proposed. Results are validated by means of simulation results carried out on a 22 nm CMOS FD-SOI technology.