TID Degradation Mechanisms in Gate-All-Around Silicon Nanowire FETs

The susceptibility of nanowire FETs (NWFETs) to total ionizing dose (TID) is investigated via the technology computer-aided design (TCAD) models that are validated via comparison with experimental studies. The simulated contributions of trapped charge in the gate oxide, spacer, and shallow trench isolation (STI) to performance degradation are compared with the measured TID response of NWFETs to identify the dominant source of TID degradation. Results indicate that degradation in both the gate oxide and the spacer are dominant contributor to degradation in p-type NWFETs, while the spacer is the main contributor for n-type NWFETs. An analysis of the impact of spacer length on the TID response of devices indicates that spacers may become less important in gate-all-around (GAA) technology. Results are compared with previous technology nodes, highlighting the reduced role that STI and spacer dielectrics play in NWFET TID degradation.