A high-voltage monolithic active pixel sensor, designed to be compatible with standard deep sub-micron CMOS production lines, is described. The device can support a reverse bias voltage of -180 V and combines small collection electrodes with full wafer depletion, demonstrated up to a thickness of 300 μm. Test structures consisting of matrices with an area of 2 × 2 mm embedding 576 pixels with 50 μm pitch have been fabricated in a 110 nm CMOS process. The sensor concept is discussed and experimental measurements obtained on first prototypes are presented.
Depleted MAPS on a 110 nm CMOS CIS Technology
Croci, Tommaso;Mattiazzo, Serena;Giubilato, Piero
2019
Abstract
A high-voltage monolithic active pixel sensor, designed to be compatible with standard deep sub-micron CMOS production lines, is described. The device can support a reverse bias voltage of -180 V and combines small collection electrodes with full wafer depletion, demonstrated up to a thickness of 300 μm. Test structures consisting of matrices with an area of 2 × 2 mm embedding 576 pixels with 50 μm pitch have been fabricated in a 110 nm CMOS process. The sensor concept is discussed and experimental measurements obtained on first prototypes are presented.
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