This article derives models for stationary noise propagation in multi-sampled control systems, taking decimation into account. It is explained how the decimation is either included deliberately, in case of multi-rate control, or inherently by the modulator, in case of multi-sampled pulsewidth modulation (MS-PWM). In the latter case, the decimation rate is determined by the switching frequency and the number of pulsewidth modulation (PWM) carriers. The proposed models are then used for digital filter design, with a goal of suppressing the decimation-related aliasing and attenuating noise, while considering the imposed impact on the dynamic response. The theory is verified in simulations and experimentally, confirming the assumed decimation mechanisms as well as the potentiality of MS-PWM to jointly enable high-bandwidth control and strong noise suppression. The experimental measurements are conducted on two hardware prototypes, comprising two-level and three-level dc-dc buck converters.
Models for Stationary Noise Propagation in Multi-sampled PWM Power Electronic Control Systems With Decimation
Cvetanovic, R;Mattavelli, P;Buso, S
2023
Abstract
This article derives models for stationary noise propagation in multi-sampled control systems, taking decimation into account. It is explained how the decimation is either included deliberately, in case of multi-rate control, or inherently by the modulator, in case of multi-sampled pulsewidth modulation (MS-PWM). In the latter case, the decimation rate is determined by the switching frequency and the number of pulsewidth modulation (PWM) carriers. The proposed models are then used for digital filter design, with a goal of suppressing the decimation-related aliasing and attenuating noise, while considering the imposed impact on the dynamic response. The theory is verified in simulations and experimentally, confirming the assumed decimation mechanisms as well as the potentiality of MS-PWM to jointly enable high-bandwidth control and strong noise suppression. The experimental measurements are conducted on two hardware prototypes, comprising two-level and three-level dc-dc buck converters.Pubblicazioni consigliate
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