Architettura di Flip Flip efficiente e resistente ai "soft-errors" e metofologia di progettazione per sistemi digitali CMOS,

Radiation induced soft errors is a well-known problem in electronic designs. It happens due to ionizing radiation interaction with the electronic device resulting into temporary change of state. The change of state could be due radiation particle directly affecting the storage element known as single event upset (SEU) or a single event transient (SET) in any combinational element getting latched by storage element. With shrinking feature size and increase in packing density of CMOS devices used in electronics system, probability of occurrence of soft errors has gone up. Specific radiation hardening design and methodologies are required to make the electronic system tolerant to radiation induced faults. In this thesis work, I study the radiation induced effects on CMOS circuits and various methods used to assess and mitigate them. I investigated various soft error tolerant flip-flop and latch circuits which are the most basic sequential elements used in every electronic digital system. Each of these circuits have their own merits and demerits. These hardening techniques normally improves the radiation tolerance but degrades other parameters like area, power dissipation and speed of the circuit. Depending on the target application and radiation environment particular hardened circuits and methods are used to meet the acceptable failure rate with least possible penalty. Moreover, design and implementation cost is another factor which is considered. A new low power robust flip-flop circuit is discussed in detail, targeted for low to medium radiation tolerance applications which promises to improve power dissipation penalty. Another new flip-flop circuit and design methodology targeted for high radiation environment applications is discussed which employs spatial and temporal redundancy to overcome both SEU and SET faults and has embedded timing pre-error detection capability. This timing error sensing capability can be used at system level in many ways, to make system more efficient and to make it adaptable to changing operating environment and long-term device degradations. Both designs were implemented and validated in ST 90nm BCD technology process using CMOS devices using two test-chips. Complete design, implementation, simulation and test details are presented in this work. Comparative analysis is done with respect to standard D flip-flop circuit and other popular hardening strictures such as dual interlocked cell (DICE) based flip-flop, and triple modular redundancy (TMR) flip-flop. Proposed design appears to provide an efficient alternative to soft error tolerant designs.