Total Ionizing Dose Degradation Mechanisms in Nanometer-scale Microelectronic Technologies

Total ionizing radiation may affect the electrical response of the electronic systems, inducing a variation of their nominal electrical characteristics and degrading their performance. The study of the radiation effects in microelectronic devices is essential in the space, avionic, and ground level applications affected by artificial and/or natural radiation environments, where the reliability is one of the most important requirements. In this thesis work, I investigate the total ionizing dose (TID) degradation mechanisms in several modern nanometer-scale technology nodes. The analysis of the TID mechanisms is focused on the evaluation of measurable effects affecting the electrical response of the devices and on the identification of the microscopical nature of the radiation-induced defects. Several transistors, based on MOSFET and FinFET structures of different manufacturers, have been tested under ionizing radiation at several temperatures, bias configurations, annealing conditions, and transistor dimensions. Technologies dedicated to high energy physics experiments have been tested at ultra-high doses, never explored thus far. Several different techniques, as DC static characterization, charge pumping and low frequency noise measurements as well as Technology Computer-Aided Design simulations, were used to identify location, density and energy levels of the radiation-induced defects. The experimental measurements presented in this work provide a unique and comprehensive set of data, pointing out the strong influence of the scaling down to the TID-induced phenomena in deeply scaled microelectronic transistors. TID mechanisms have been studied following the technological evolution of the devices at various nodes: 150 nm Si-based MOSFET, 65 nm Si-based MOSFET, 28 nm Si-based MOSFET with HfO2 gate dielectric, 16 nm InGaAs-based FinFET with HfO2/Al2O3 gate dielectrics and, at last, a new laboratory grade InGaAs MOSFET with Al2O3 gate dielectric. All results confirm the high TID tolerance of the thin gate oxide of nanoscaled technologies, due to the reduced charge trapping in the gate dielectric. However, the aggressive downsizing of devices has led to new TID-induced effects related to other thick oxides and modern production processes, e.g., shallow trench insulations oxides, spacer dielectrics, and halo implantations. In the case of compound semiconductors, I have observed how defects are associated to the properties at the interface between III-V materials and high-k dielectrics. New TID mechanisms appear, showing their dependence on irradiation/annealing bias condition, channel length, and channel width.