Characterization and modeling of GaN-based transistors for power applications

GaN-based devices have emerged as a promising solution for power management applications. The intrinsic physical properties of the Gallium Nitride are exploited in order to considerably improve the efficiency and to reduce the volume of the next generation power switching converters. The wide energy gap allows to fabricate high voltage-rate devices with a reduced area consumption, whereas the high mobility guarantees a considerably low on-Resistance of the transistor. Moreover, thanks to the reduced parasitic capacitances, the operating frequency of the devices can be higher than conventional Silicon based transistors. In order to ensure a wide spreading of Gallium Nitride technology in the power transistors market, the price of the devices needs to be kept as low as possible. The costs of native substrates for the fabrication of GaN transistors are nowadays prohibitive, so that the epitaxial growth of Gallium Nitride on Silicon substrates has been developed. GaN-on-Silicon is the most suitable technology to fabricate GaN-based devices on a cheap and large area wafers (up to 200 mm), resulting in a significant reduction of the production costs. On the other hand, growing GaN on a foreign substrate results in high dislocation and defect densities which could affect the performance of the devices in terms of both losses and reliability issues. A so-called “buffer decomposition experiment” allowed to evaluate the role of the different layers which compose the vertical stack of a GaN-on-Silicon wafer by characterizing samples obtained by stopping the epitaxial growth at different stages of the process. It is demonstrated that both the thickness and the composition of the epitaxial stack, beside enhancing the breakdown voltage, improve the material quality by limiting the propagation of defects and dislocations. Moreover, a study on the reliability of the Aluminum Nitride layer grown on silicon is presented, showing that the AlN fails due to a wear-out process following a Weibull distribution. Furthermore, an extensive analysis on the reliability of the GaN-on-Silicon vertical stack is presented, as well as a systematic study on the failure statistic. It is shown that the time to failure of the GaN-on-Silicon stack is Weibull distributed, and, although it is weakly temperature-activated, it exponentially depends on the applied voltage. Moreover, the expected lifetime of the tested devices at the operating voltage is extracted. Aiming to further improve the performance of lateral High Electrons Mobility Transistors (HEMTs) in terms of vertical robustness and losses reduction, the impact of the resistivity of the silicon substrates has been evaluated. It is shown that highly resistive p-doped substrate results in a plateau region in the IV characteristic which considerably increases the vertical breakdown voltage of the devices. Nevertheless, the existence of a trade-off between the vertical robustness and the stability of the threshold voltage is demonstrated. A set of electrical characterization ascribes the threshold voltage shift to the positive backgating effect possibly related to the capacitive coupling of the partially depleted substrate which only occurs if lowly p-doped silicon is used. The origin of the plateau region is further investigated by means of a set of TCAD simulations, allowing to develop a two-diodes model which confirms the hypothesis on the substrate depletion. Even if stable and reliable lateral HEMTs are commercially available, their operating voltage is limited to ~ 900 V. In order to expand the applications field of the GaN-based devices to higher operating voltage, different device concepts have been developed so far. A promising solution is represented by (semi-)vertical trench gate devices, which are characterized by a thick drift layer where the OFF-state electric field spreads vertically in a bulky region, thus avoiding surface effects. Thanks to the vertical architecture, the OFF-state breakdown only depends on the thickness of the epitaxial stack, thus allowing to reach high breakdown voltages with a limited area consumption. Since the carriers must flow vertically, the gate of the devices lies in an etched trench, and it consists of a Metal Oxide Semiconductor (MOS) system. Within this thesis the gate leakage is deeply studied on devices with different gate dielectric, by means of electrical characterizations performed with different connection configurations and different bias polarities. Moreover, the gate capacitance is analytically calculated, and the experimental behavior observed for the Gate-Source and Gate-Drain capacitances over the applied voltage is discussed and modeled considering the GaN bias condition close to the dielectric interface. Lastly, a preliminary dielectric trap characterization is performed by evaluating the capacitance hysteresis induced by the electric field within different gate oxide materials. The last section of this work presents a custom setup developed for the characterization of the threshold voltage variations over the time. The stability of the threshold voltage is fundamental for allowing a device to operate properly in a switching converter. Standard pulsed systems used for the characterization of the threshold voltage allow to evaluate the impact of the bias level on the threshold variation, but no details on the time evolution can be obtained. The presented threshold transient setup monitors the threshold voltage variation over a wide time-interval, ranging from 10 µs to 100 s, allowing the analysis of the trapping and detrapping kinetics. Moreover, by monitoring the transient variation as a function of the temperature it is possible to full characterize (energy level and cross section) the traps involved in the observed instabilities.