In this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal.
Understanding the impact of split-gate LDMOS transistors: Analysis of performance and hot-carrier-induced degradation
Magnone P.
;Pistollato S.;
2021
Abstract
In this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device is also investigated, highlighting the influence of the split-gate voltage. This work allows identifying a tradeoff between the performance and reliability of the component, which is controlled by the voltage applied to the split-gate terminal.File | Dimensione | Formato | |
---|---|---|---|
magnone.pdf
accesso aperto
Tipologia:
Preprint (submitted version)
Licenza:
Creative commons
Dimensione
502.52 kB
Formato
Adobe PDF
|
502.52 kB | Adobe PDF | Visualizza/Apri |
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.