This paper defines the latch-up failure mechanism in CMOS, analyzes methods and tools to detect it, including microscopy techniques capable of identify parasitic latch-up paths; test structures for the study of latch-up sensitivity and methods to prevent latch-up are also described.
Latch-up in CMOS integrated circuits
ZANONI, ENRICO
1989
Abstract
This paper defines the latch-up failure mechanism in CMOS, analyzes methods and tools to detect it, including microscopy techniques capable of identify parasitic latch-up paths; test structures for the study of latch-up sensitivity and methods to prevent latch-up are also described.
File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
