Spice Simulation of Latch-up Anomalous Effects Observed By Electrical Measurements and Ir Microscopy

Pulsed overvoltage tests have identified anomalies in the electrical characteristics of latch-up in CMOS ICs and 'window' effects, while infra-red (IR) microscopy revealed that latch-up current switching is due to competition between different latch-up paths. The SPICE simulation of a simple, lumped, equivalent circuit model, comprising two or more parasitic structures, allows anomalous effects to be produced and helps in the understanding of latch-up triggering mechanisms. Parasitic bipolar transistors connected to the I/O structure, not involved in latch-up in steady-state, are shown to play a major role in latch-up triggering and in causing anomalous effects.