ESD in Smart Power Processes

Electrostatic Discharge (ESD) is today one of the major concern for Integrated Circuits (IC) chip quality. Amerasekera and Duvurry [1] have identified ESD as one of the most common failure mode in silicon ICs: roughly 10 % of the failing parts is attributed to ESD event. Vinson and Liou [2] reported that roughly 20 % of the field return failures may be attributed to ESD while Wagner et al. [3] identified ESD as being the cause of greater than 25% of the failures encountered. Chip redesign and complete new mask set are often required to solve ESD weakness detected in the product development phase. Costs associated with these values are huge, but even more difficult to measure are the intangible costs related to delays and to the loss of customer confidence caused by failed products. Advanced process technologies did have a severe impact on ESD robustness: linear dimensions (channel lengths, gate oxide thickness and junction depth) scaling in new processes comes together with supply voltage reduction but “unfortunately” people do not scale accordingly! For this reason the ESD level requested is not reduced in new technologies and many new applications, made possible by advanced IC processes, require even increased ESD performances. Furthermore advanced technologies allow designers to realize very complex system on chip (SOC) with very large pin counts. The bonding pad pitch has to scale properly and the total area available for ESD protection circuit is going to become smaller and smaller.