The purpose of this work was to study the influence of different layout parameters on the electrical performances and Time-To-Latch-Up (TTLU) by means of the injection of substrate current on SCR devices to be used as ESD protection structures for the 65 nm Flash memory technology platform. Low (1.2 V) and high (5.0 V) voltage class devices were studied in DC and 100 ns TLP regimes, and an ad hoc setup was developed to investigate TTLU as a function of the injected current needed to Latch-Up HV-SCRs. Results were then compared to 2D device simulations.
Time-To-Latch-Up investigation of SCR devices as ESD protection structures on 65 nm technology platform
TAZZOLI, AUGUSTO;MENEGHESSO, GAUDENZIO
2010
Abstract
The purpose of this work was to study the influence of different layout parameters on the electrical performances and Time-To-Latch-Up (TTLU) by means of the injection of substrate current on SCR devices to be used as ESD protection structures for the 65 nm Flash memory technology platform. Low (1.2 V) and high (5.0 V) voltage class devices were studied in DC and 100 ns TLP regimes, and an ad hoc setup was developed to investigate TTLU as a function of the injected current needed to Latch-Up HV-SCRs. Results were then compared to 2D device simulations.
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