IESURUM, AGATA

Nome completo

IESURUM, AGATA

Afferenza

Università di Padova

Mostra records

Risultati 1 - 9 di 9 (tempo di esecuzione: 0.018 secondi).

A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS

2022 Iesurum, Agata; Manente, Davide; Padovan, Fabio; Bassi, Matteo; Bevilacqua, Andrea

A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs

2024 Grimaldi, Luigi; Iesurum, Agata; Boi, Giovanni; Versolatto, Fabio; Steffan, Giovanni; Padovan, Fabio; Koltsov, Heorhii; Bevilacqua, Andrea; Cherniak, Dmytro

A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching

2022 Dartizio, Simone Mattia; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

2023 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler

2022 Buccoleri, Francesco; Dartizio, Simone M.; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Bevilacqua, Andrea; Bertulessi, Luca; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time

2022 Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore

A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies

2024 Tomasin, Lorenzo; Iesurum, Agata; Gobbo, Andrea; Neviani, Andrea; Bevilacqua, Andrea

Analysis and Design of Coupled PLL-Based CMOS VCOs

2024 Iesurum, A; Manente, D; Padovan, F; Bassi, M; Bevilacqua, A

Analysis and Design of mm-Wave Harmonic Oscillators in CMOS Technology

2024 Iesurum, Agata

Titolo	Data di pubblicazione	Autori	Rivista	Serie	Titolo libro
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS	2022	Iesurum, AgataManente, DavidePadovan, FabioBassi, MatteoBevilacqua, Andrea + -	-	-	ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)
A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs	2024	Grimaldi, LuigiIesurum, AgataBoi, GiovanniVersolatto, FabioSteffan, GiovanniPadovan, FabioKoltsov, HeorhiiBevilacqua, AndreaCherniak, Dmytro + -	-	-	2024 IEEE European Solid-State Electronics Research Conference (ESSERC)
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching	2022	Dartizio, Simone MattiaBuccoleri, FrancescoTesolin, FrancescoAvallone, LucaSanticcioli, AlessioIesurum, AgataSteffan, GiovanniCherniak, DmytroBertulessi, LucaBevilacqua, AndreaSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore + -	-	-	2022 IEEE International Solid- State Circuits Conference (ISSCC)
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner	2023	Buccoleri, FDartizio, SMTesolin, FAvallone, LSanticcioli, AIesurum, ASteffan, GCherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S + -	IEEE JOURNAL OF SOLID-STATE CIRCUITS	-	-
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler	2022	Buccoleri, FrancescoDartizio, Simone M.Tesolin, FrancescoAvallone, LucaSanticcioli, AlessioIesurum, AgataSteffan, GiovanniBevilacqua, AndreaBertulessi, LucaCherniak, DmytroSamori, CarloLacaita, Andrea L.Levantino, Salvatore + -	-	-	Proceeding of the 2022 IEEE Custom Integrated Circuits Conference (CICC)
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time	2022	Dartizio, Simone M.Buccoleri, FrancescoTesolin, FrancescoAvallone, LucaSanticcioli, AlessioIesurum, AgataSteffan, GiovanniCherniak, DmytroBertulessi, LucaBevilacqua, AndreaSamori, CarloLacaita, Andrea L.Levantino, Salvatore + -	IEEE JOURNAL OF SOLID-STATE CIRCUITS	-	-
A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies	2024	Tomasin, LorenzoIesurum, AgataGobbo, AndreaNeviani, AndreaBevilacqua, Andrea + -	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS	-	-
Analysis and Design of Coupled PLL-Based CMOS VCOs	2024	Iesurum, AManente, DPadovan, FBassi, MBevilacqua, A + -	IEEE JOURNAL OF SOLID-STATE CIRCUITS	-	-
Analysis and Design of mm-Wave Harmonic Oscillators in CMOS Technology	2024	IESURUM, AGATA	-	-	-