Asymmetric Digital Dual-Edge Modulator for Dynamic Performance Improvement of Multiloop-Controlled VSI

This article proposes the architecture and a graphical-based analysis for a digital asymmetric dual edge (ADE) carrier-based pulsewidth modulator. In its digital version, it retains some advantages offered by the analog implementation. Indeed, in single-sampling operation, the phase delay introduced by this modulator is always less than or equal to the one obtained with the trailing-triangle edge (TTE) carrier. Moreover, by combining the advantages given by the ADE carrier and the double sampling of the modulating signal, it is possible to realize a digital modulator with a null phase delay. Since the proposed ADE-carrier-based digital pulsewidth modulator (DPWM) operates at a variable switching frequency, synchronization strategies between the carrier and the sampling instants may be required for some applications. Reliable synchronism correction architectures are, therefore, proposed and discussed. The developed model is validated through simulation and experimentally on a 27.5-kHz 9-kW single-phase voltage-source inverter case study. The experimental tests include a comparison with the DPWM architecture based on the TTE carrier.