Multi-sampling Asymmetric Dual-Edge Digital Pulse-width Modulator

Digital controls are generally characterized by significant phase delays due to the analog-to-digital conversion process, sampling time, algorithm computation time, and the digital pulse-width modulator's architecture. Usually, the delay introduced by the latter has a more significant impact than previous ones, especially when approaching the switching frequency. The multi-sampling operation is largely adopted to reduce this delay. Recently proposed, double-sampling asymmetrical dual-edge (ADE) carrier-based digital pulse-width modulators (DPWM) have proven to operate with zero phase delay. Therefore, the multi-sampling architecture might provide even better results. Unfortunately, its documented operating point dependence does not allow such modulators to be used effectively. This article examines an improved multi-sampling ADE-DPWM architecture where the dependency on the operating point is significantly reduced. This manuscript also includes an accurate small-signal transfer function model. The proposed architecture and the developed small-signal model are validated in simulation and experimentally. In addition, experimental tests on a multi-loop voltage-controlled single-phase voltage-source inverter revealed the advantages of the proposed architecture over the more traditional DPWM one based on a trailing-triangle edge carrier.