Innovative Digital dc-dc Architectures for High-Frequency High-Efficiency Applications

The new generation of automotive controllers requires a space-constrained and high-efficiency step-down architecture. Hence, recently a potential alternative for the conventional step-down topologies is highly demanded. The new architecture should meet the high power density, high efficiency, wide operating ranges, high EMI capabilities, and low-cost requirements. This thesis, developed at the University of Padova and sponsored by Infineon Technologies, aims at investigating potential candidate topologies for automotive step-down conversion capable of eliminating or offsetting some of the common shortcomings of conventional solutions currently in use. Many research effort is paid for the soft switching quasi-resonant topologies in order to miniaturize the passive components through the switching frequency increase. However, the variable switching frequency, increased components count, and narrow operating ranges prevent the wide adoption of the quasi-resonant topologies in the target application. The first objective of this project is to investigate the quasi-resonant buck converter topology in order to stand on the limitations and operating conditions boundaries of such topology. The digital efficiency optimization technique, which is developed in this work, extends the operating ranges in addition to reduce operating frequency variations. On the other hand, the multilevel hybrid topologies are potentially able to meet the aforementioned requirements. By multiplying ripple frequency and fractioning voltage across the switching node the multilevel topologies have the direct advantage of reduced passive components. Moreover, multilevel topologies have many other attractive features include reduced MOSFET voltage rating, fast transient response, a Buck-like wide range voltage conversion ratio, and improved efficiency. These features candidate the multilevel topologies, in particular, the three-level flying-capacitor converter, as an innovative alternative for the conventional topologies for the target application. Accordingly, the three-level flying-capacitor converter (3LFC) is investigated as a second objective for this project. Flying-capacitor (FC) voltage balancing in such topology is quite challenging. The 3LFC under valley current mode control shows an interesting performance, where the FC voltage is self-balanced. In this work, the stability of the converter under valley and peak current mode control is studied and a simplified stability criterion is proposed. The proposed criterion address both current loop static stability and FC voltage stability. The valley current mode modulator results to be inherently stable as soon as the current static instability is compensated with an external ramp. On contrary, the FC voltage in peak current mode control (P-CMC) will never be balanced unless the converter operated with relatively high static peak-to-peak inductor current ripple. Since P-CMC has an inherent over-current protection feature, P-CMC based architectures are widely used in the industrial applications. However, in practice the peak current controlled three-level converter is inherently unstable. Consequently, the instability of the P-CMC 3LFC is addressed. A sensorless stabilizing approach, with two implementation methodologies, is developed in this work. The proposed technique eliminates the instability associated with the FC voltage runaway, in addition to FC voltage self-balancing. Moreover, the proposed methodology offers reduced size, less complexity, and input voltage independent operation. Besides, the proposed approach can be extended to system with a higher number of voltage levels with minimal hardware complexity. The proposed techniques and methodologies in this work are validated using simulation models and experimentally. Finally, in the conclusions the results of the Ph.D. activity are summarized and recommendations for the further development are outlined.