A delay line was developed on a VLSI gate array for drift time measurements on muon chambers of the ZEUS detector at HERA. It consists of 80 cells featuring a 3 ns/cell propagation time; at the start a short pulse is injected into the line and at the stop the status of the line is latched into a 10 byte register. An r.m.s. resolution better than 1 ns was obtained with this reasonably low-cost TDC.
A DELAY-LINE ON A VLSI GATE ARRAY AS A TIME DIGITIZER
BRUGNERA, RICCARDO;CARLIN, ROBERTO;STANCO L;STROILI, ROBERTO
1994
Abstract
A delay line was developed on a VLSI gate array for drift time measurements on muon chambers of the ZEUS detector at HERA. It consists of 80 cells featuring a 3 ns/cell propagation time; at the start a short pulse is injected into the line and at the stop the status of the line is latched into a 10 byte register. An r.m.s. resolution better than 1 ns was obtained with this reasonably low-cost TDC.File in questo prodotto:
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