This paper focuses on the non-inverting buckboost converter supplying an adjustable DC voltage to a WCDMA RF power amplifier (RFPA) in order to improve the system efficiency under different transmitted RF power levels. It is shown that precise output voltage positioning and low output voltage ripple over a wide output voltage range, including buck, boost and buck/boost transition modes, can be accomplished using 1_-A modulation in combination with a small, low-power, low-resolution DPWM core. A two-mode digital controller is presented, in which the compensator parameters are changed upon buck/boost mode transitions in order to improve closed-loop dynamic performance. Results are verified on an experimental test bed that consists of a prototype 0.5 Fun CMOS chip that integrates power MOSFETs, drivers and dead-time control logic, and the digital controller implemented on an FPGA. The worst case output voltage ripple over buck, boost and mode transition region is within 35mV and the output voltage transients meet the WCDMA RFPA settling time requirements.
Sigma-Delta Modulated Digitally Controlled Non-Inverting Buck-Boost Converter for WCDMA RF Power Amplifiers
CORRADINI, LUCA;
2009
Abstract
This paper focuses on the non-inverting buckboost converter supplying an adjustable DC voltage to a WCDMA RF power amplifier (RFPA) in order to improve the system efficiency under different transmitted RF power levels. It is shown that precise output voltage positioning and low output voltage ripple over a wide output voltage range, including buck, boost and buck/boost transition modes, can be accomplished using 1_-A modulation in combination with a small, low-power, low-resolution DPWM core. A two-mode digital controller is presented, in which the compensator parameters are changed upon buck/boost mode transitions in order to improve closed-loop dynamic performance. Results are verified on an experimental test bed that consists of a prototype 0.5 Fun CMOS chip that integrates power MOSFETs, drivers and dead-time control logic, and the digital controller implemented on an FPGA. The worst case output voltage ripple over buck, boost and mode transition region is within 35mV and the output voltage transients meet the WCDMA RFPA settling time requirements.Pubblicazioni consigliate
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