A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35-μm CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 μA, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker.

A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers

GEROSA, ANDREA;NEVIANI, ANDREA
2004

Abstract

A programmable-gain preamplifier and filter for detection of spontaneous heart activity in an implantable cardiac pacemaker is presented. The system is fully integrated in a standard 0.35-μm CMOS technology, including all auxiliary circuits. Two channels are available in order to process both atrial and ventricular signals. CMOS translinear circuits, with particular emphasis on log-domain techniques, have been exploited in order to contain current consumption and to allow correct operation with a reduced supply voltage, due to battery discharging. Indeed, the realized system can operate down to 1.8 V of supply voltage and dissipates at most 1.8 μA, granting at least 47 dB of dynamic range (DR) for the atrial chain, which is compatible with advanced digital sensing. Current consumption can be further reduced at the expense of DR if a simpler sensing like peak detection is adopted. All system performance have been verified by measurements results and are compatible with the requirements of cardiac pacemakers. This work, therefore, demonstrates how a proper design approach, exploiting low-power and low-voltage techniques, allows one to optimize performance for the cardiac pacemaker.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/1349240
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